With the recent tendency towards the reduction of the size and the enhancement of the properties of electronic apparatus, it has been required that semiconductor apparatus and multi-layer printed-wiring boards on which they are mounted have reduced size, reduced thickness, high performance and high reliability. In order to meet these requirements, the mounting method has been switched from pin insertion method to surface mount method. In recent years, a mounting method called bare chip mounting involving the direct mounting of chips on printed circuit board has been studied.
In accordance with the bare chip mounting method, silicon chips are directly mounted on a printed circuit board. However, since silicon chips exhibit a thermal expansion coefficient of from 3 to 4 ppm/.degree. C. and printed circuit boards exhibit a thermal expansion coefficient of from 15 to 20 ppm/.degree. C., the resulting difference in thermal expansion coefficient between the two components causes the generation of stress, lowering the reliability in connection of mounted structure. In the case of flip chip mounting, such a stress causes destruction of connection, causing defects such as malconduction.
In order to relax such a stress, it is practiced to inject an adhesive called underfill into the gap between the chip thus mounted and the circuit board. As such an underfill there is used a thermosetting resin. The purpose of this underfill is to disperse the stress due to the difference in thermal expansion between chip and circuit board.
In order to relax the stress of the printed-wiring board itself, a multi-layer printed-wiring board is proposed comprising an absorption layer for absorbing interlayer shear strain provided interposed between layers of the multi-layer printed-wiring board and having a stepwise vertical change in the horizontal thermal expansion coefficient of the each layer (as disclosed in JP-A-7-297560 (The term "JP-A" as used herein means an "unexamined published Japanese patent application")).
On the other hand, with the recent enhancement of performance of electronic apparatus, semiconductor chips used tend to generate raised heat. The heat accumulated in the chips causes a drop of reliability of the chips. Thus, it has been practiced to provide chips or packages with a heat dissipation fin or heat sink which is air-cooled by a fan.
With the rise in the number of I/O pins on chips, it has been more and more required that the board on which chips are mounted be formed in multi-layers. As such a multi-layer wiring board there has been proposed a built-up multi-layer wiring board obtained by alternatingly laminating an insulating layer made of a photosensitive resin and a conductor layer formed by plating or vacuum evaporation on one or both sides of a board. As another multi-layer wiring board there has been proposed a multi-layer wiring board obtained by repeating a procedure involving the formation of an electrically conductive paste on one side (copper-clad surface) of a copper-clad glass epoxy laminate as protrusions using a dispenser and pressing of an adhesive sheet and a copper foil on the laminate (as disclosed in JP-A-8-288649). As a further multi-layer wiring board there has been proposed a multi-layer wiring board obtained by alternatingly laminating an insulating layer and a wire conductor on an Ni--Fe alloy as a substrate or by forming a solder pad on the surface of the multi-layer wiring board by photoengraving process, and then integrating the laminate under heating and pressure (as disclosed in JP-A-61-212096).
However, even if stress is relaxed by the foregoing means, the mounted structure or circuit board leaves something to be desired in reliability in connection. In order to secure higher reliability, it is required that heat generated by chips be dissipated or the thermal expansion coefficient of the circuit board be lowered.
Further, since the modern electronic apparatus must meet growing demand for portability and hence reduction of size, thickness and weight, the foregoing heat dissipation structure has been used less and less.
The above multi-layer wiring boards which meet the demand for the increase of the number of I/O pins on chips find various difficulties in production. In other words, the foregoing built-up multi-layer wiring board finds various difficulties. For example, such a built-up multi-layer board must be prepared at a complicated process involving a large number of steps. Further, such a built-up multi-layer board can be prepared in only a low yield. Thus, such a built-up multi-layer board cannot be delivered rapidly. The foregoing other multi-layer wiring boards comprising protrusions formed of an electrically conductive paste by a dispenser or the like find difficulties in reliability in connection, connecting resistance, etc. Further, such multi-layer wiring boards can be hardly applied to fine circuits. Moreover, such multi-layer wiring boards must be repeatedly pressed by times corresponding to the number of required layers to realize the multi-layer form, requiring much time for production. Further, the foregoing other multi-layer wiring boards comprising an Ni--Fe alloy as a substrate require the use of vacuum evaporation method or sputtering method to form a thin metal layer. Thus, these multi-layer wiring boards can be obtained only at a reduced productivity and hence at a raised cost.